netgen - LVS netlist comparison tool for VLSI
Description:
Netgen is a tool for comparing netlists, a process known as LVS, which stands for "Layout vs. Schematic". This is an important step in the integrated circuit design flow, ensuring that the geometry that has been laid out matches the expected circuit. The greatest need for LVS is in large analog or mixed-signal circuits that cannot be simulated in reasonable time. Even for small circuits, LVS can be done much faster than simulation, and provides feedback that makes it easier to find an error than does a simulation.
Homepage: http://opencircuitdesign.com/netgen
License: GPL+
Vendor: Fedora Project
Packages
| netgen-1.3.7-12.fc8.i386 [149 KiB] |
Changelog by Chitlesh Goorah (2007-08-23):
- complying to freedesktop policies - categories |